1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to formation of three-dimensional memory modules.
2. Description of Related Art
As densities of semiconductor memories increase, two-dimensional structures are no longer able to meet specified requirements. Accordingly, three-dimensional memories are becoming known, although manufacturing processes for fabricating three-dimensional memories pose special problems. One approach to creating memory structures in three dimensions involves forming memory elements disposed in horizontal layers of staircase structures and then providing access to the conducting surface levels of the layers by connecting the layers to a control layer with vertical conducting elements disposed in contact openings. The staircase structures may be formed by first laying down alternating layers of insulating and conducting material. Sequential mask/photo/etch steps can then be performed with photoresist being incrementally peeled back between etch steps. Performing etches of monotonically increasing depth creates multiple steps of staircase structures. When the number of etch steps is large, this approach forms large discontinuities between levels of adjacent surfaces in semiconductor structures. These large discontinuities may cause critical dimensions to be compromised, thereby reducing a contact patterning overlay margin and creating an unwanted etch-through issue.
A need thus exists in the prior art for multilayer semiconductor structures that do not exhibit large discontinuities between adjacent conducting surface levels. A further need exists for a method of forming such multilayer semiconductor structures.